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HCS32MS
Data Sheet April 11, 2007 FN3057.1
Radiation Hardened Quad 2-Input OR Gate
The Intersil HCS32MS is a Radiation Hardened Quad 2-Input OR Gate. A low on both inputs forces the output to a low state. The HCS32MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS32MS is supplied in a 14 Ld Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
Features
* 3 Micron Radiation Hardened SOS CMOS * Total Dose 200k RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) * Latch-Up Free Under Any Conditions * Military Temperature Range: -55C to +125C * Significant Power Reduction Compared to LSTTL ICs
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. # D14.3
* DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels * VIL = 30% of VCC Max * VIH = 70% of VCC Min * Input Current Levels Ii 5A @ VOL, VOH
HCS32DMSR Q 5962R95 -55C to +125C 14 Ld SBDIP 78101VCC
HCS32KMSR Q 5962R95 -55C to +125C 14 Ld Ceramic K14.A 78101VXC Flatpack HCS32D/ Sample HCS32K/ Sample HCS32HMSR +25C +25C +25C 14 Ld SBDIP 14 Ld Ceramic Flatpack Die
Functional Diagram
An (1, 4, 9, 12) Yn
Intersil Pb-free hermetic packaged products employ SnAgCu or Au termination finish, which are RoHS compliant termination finishes and compatible with both SnPb and Pb-free soldering operations. Ceramic dual in-line packaged products (CerDIPs) do contain lead (Pb) in the seal glass and die attach glass materials. However, lead in the glass materials of electronic components are currently exempted per the RoHS directive. Therefore, ceramic dual inline packages with Pb-free termination finish are considered to be RoHS compliant.
(3, 6, 8, 11) Bn (2, 5, 10, 13)
TABLE 1. TRUTH TABLE INPUTS An L L H H NOTE: Bn L H L H OUTPUTS Yn L H H H
L = Logic Level Low, H = Logic level High
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1995, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HCS32MS Pinouts
HCS32MS 14 LD SBDIP TOP VIEW
A1 1 B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 A1 B1 Y1 A2 B2 Y2 GND
HCS32MS 14 LD CERAMIC FLATPACK TOP VIEW
1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3
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FN3057.1 April 11, 2007
HCS32MS
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VCC +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . 10mA DC Drain Current, Any One Output . . . . . . . . . . . . . . . . . . . . 25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG). . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . . +265C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Notes 1, 2) JA JC SBDIP Package . . . . . . . . . . . . . . . . . 74C/W 24C/W Ceramic Flatpack Package . . . . . . . . . 116C/W 30C/W Maximum Package Power Dissipation at +125C Ambient SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . . .0.43W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/C Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . .8.6mW/C
Operating Conditions
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max Operating Temperature Range (TA). . . . . . . . . . . . .-55C to +125C Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . .70% of VCC to VCC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
DC Electrical Electrical Performance Characteristics
GROUP A SUBGROUPS 1 2, 3 1 2, 3 1 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2, 3 7, 8A, 8B LIMITS TEMP (C) +25 +125, -55 +25 +125, -55 +25 +125, -55 +25, +125, -55 +25, +125, -55 MIN 4.8 4.0 -4.8 -4.0 MAX 10 200 0.1 0.1 0.5 5.0 UNITS A A mA mA mA mA V V V V A A -
PARAMETER Quiescent Current
SYMBOL ICC
TEST CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V
Output Current (Sink)
IOL
Output Current (Source)
IOH
Output Voltage Low
VOL
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V, IOH = -50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOH = -50A, VIL = 1.65V
+25, +125, -55 VCC - 0.1 +25, +125, -55 VCC - 0.1 +25 +125, -55 +25, +125, -55 -
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 0.70 (VCC), VIL = 0.30(VCC), (Note 3)
Noise Immunity Functional Test
FN
NOTES: 3. This is just to show continuing notes in the document. 4. This is a row format electrical spec table.
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FN3057.1 April 11, 2007
HCS32MS
AC Electrical Performance Characteristics
TEST CONDITIONS (NOTES 5, 6) VCC = 4.5V LIMITS GROUP A SUBGROUPS 9 10, 11 Data to Output TPLH VCC = 4.5V 9 10, 11 NOTES: 5. All voltages referenced to device GND. 6. AC measurements assume RL = 500, CL = 50pF, Input tr = tf = 3ns, VIL = GND, VIH = VCC. TEMP (C) +25 +125, -55 +25 +125, -55 MIN 2 2 2 2 MAX 18 20 20 22 UNITS ns ns ns ns
PARAMETER Input to Output
SYMBOL TPHL
Electrical Performance Characteristics
LIMITS PARAMETER Capacitance Power Dissipation Input Capacitance Output Transition Time NOTES: 7. The parameters listed in the Electrical Performance Characteristics are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. SYMBOL CPD TEST CONDITIONS VCC = 5.0V, f = 1MHz NOTES 7 7 CIN TTHL TTLH VCC = 5.0V, f = 1MHz VCC = 4.5V 7 7 7 TEMP (C) +25 +125, -55 +25 +25 +125 MIN MAX 6 11 10 15 22 UNITS pF pF pF ns ns
DC Post Radiation Electrical Performance Characteristics
200k RAD LIMITS PARAMETER Quiescent Current Output Current (Sink) SYMBOL ICC IOL (NOTES 8, 9) TEST CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50A VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50A VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 10) TEMPERATURE (C) +25 +25 MIN 4.0 MAX 0.2 UNITS mA mA
Output Current (Source)
IOH
+25
-4.0
-
mA
Output Voltage Low
VOL
+25
-
0.1
V
Output Voltage High
VOH
+25
VCC - 0.1
-
V
Input Leakage Current Noise Immunity Functional Test
IIN FN
+25 +25
-
5 -
A -
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FN3057.1 April 11, 2007
HCS32MS
DC Post Radiation Electrical Performance Characteristics (Continued)
Data to Output TPHL TPLH NOTES: 8. All voltages referenced to device GND. 9. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 10. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0". VCC = 4.5V VCC = 4.5V +25 +25 2 2 20 22 ns ns
Operating Specifications
PARAMETER ICC IOL/IOH GROUP B SUBGROUP 5 5 3A -15% of 0 Hour DELTA LIMIT
Applicable Subgroups
CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 11) Group B Subgroup B-5 METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11, (Note 12) ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
Subgroup B-6 Group D NOTES:
Sample/5005 Sample/5005
1, 7, 9 1, 7, 9
11. Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised. 12. Burn-In and Operating Life Test, Delta Parameters (+25C) only.
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FN3057.1 April 11, 2007
HCS32MS
Total Dose Irradiation
TEST CONFORMANCE GROUPS Group E Subgroup 2 METHOD 5005 PRE RAD 1, 7, 9 POST RAD DC Post Radiation Electrical Performance Characteristics on page 4 READ AND RECORD PRE RAD 1, 9 POST RAD DC Post Radiation Electrical Performance Characteristics on page 4 (Note 13)
NOTES: 13. Except FN test which will be performed 100% Go/No-Go.
Static And Dynamic Burn-In Test Connections
OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 14) 3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12, 13 14 -
STATIC BURN-IN II TEST CONNECTIONS (Note 14) 3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 15) NOTES: 14. Each pin except VCC and GND will have a resistor of 10k 5% for static burn-in 15. Each pin except VCC and GND will have a resistor of 1k 5% for dynamic burn-in 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10, 12, 13 -
Irradiation Test Conditions
OPEN 3, 6, 8, 11 NOTES: 16. Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. GROUND 7 VCC = 5V 0.5V 1, 2, 4, 5, 9, 10, 12, 13, 14
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FN3057.1 April 11, 2007
HCS32MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125C min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125C min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 17 and 18) 100% Dynamic Burn-In, Condition D, 240 hrs., +125C or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 18) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 19) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 20) 100% Data Package Generation (Note 21)
NOTES: 17. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 18. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 19. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 20. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 21. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
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FN3057.1 April 11, 2007
HCS32MS AC Timing Diagrams
VIH VS VIL TPLH TPHL VOH VS VOL TTLH 80% VOL 20% 80% 20% TTHL OUTPUT CL = 50pF RL = 500 INPUT CL RL
AC Load Circuit
DUT TEST POINT
VOH
OUTPUT
TABLE 1. AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V
8
FN3057.1 April 11, 2007
HCS32MS Die Characteristics
DIE DIMENSIONS: 87milsx88 mils 2.20mmx2.2mm METALLIZATION: Type: SiAl Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4milsx4mils
Metallization Mask Layout
HCS32MS
A1 (1) VCC (14) B4 (13)
B1 (2)
(12) A4
(11) Y4 Y1 (3)
A2 (4)
(10) B3
B2 (5)
(9) A3
(6) Y2
(7) GND
(8) Y3
9
FN3057.1 April 11, 2007
HCS32MS Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.235 0.125 0.030 0.008 0.270 0.026 0.005 14 MAX 0.115 0.022 0.019 0.009 0.006 0.390 0.260 0.290 0.015 0.370 0.045 0.0015 A b b1 c c1 D MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 5.97 3.18 0.76 1.27 BSC 0.20 6.86 0.66 0.13 14 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 9.91 6.60 7.11 NOTES 3 3 7 2 8 6 Rev. 0 5/18/94
e
PIN NO. 1 ID AREA
A
-A-
-B-
D
S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS
E E1 E2 E3 e k L Q S1 M N
0.050 BSC
BASE METAL b1 M M (b) SECTION A-A
(c)
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
10
FN3057.1 April 11, 2007
HCS32MS Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E
eA e eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN3057.1 April 11, 2007

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